Low-Power and Low-Area Adaptive FIR Filter Based on DA Using FPGA (International Journal of Scientific Research and Management (IJSRM), 2015)
This paper presents an innovative pipelined architecture for the implementation of adaptive filter based on distributed arithmetic (DA) with low-area, low-power. The high throughput rate of the proposed design is achieved by updating the lookup table simultaneously and parallel implementation of filtering and weight-update operations. In order to reduce the sampling period and area complexity, the proposed method uses conditional signed carry-save accumulation for the purpose of DA-based inner-product computation in the place of conventional adder-based shift accumulation. In order to reduce the power consumption, the proposed design uses a faster bit clock for carry-save accumulation but it uses a much slower clock for the remaining operations. The proposed design involves the same number of multiplexers but a smaller LUT and the number of adders used reduces to half when compared to the existing DA-based design.