Implementation of Adaptive Equalizer using FPGA (International Journal of Scientific Research and Management (IJSRM), 2015)
The quality of transmitted channel is deteriorated by channel imperfections. This results in high bit error rate at the receiver which in turn makes recovering the original signal difficult. Channel response is dynamic in nature and therefore to decrease bit error rate, adaptive equalizer is generally used at receiver end. The purpose of this paper is to present the FPGA implementation of adaptive equalizer.