[1]
J. D. Dr.satyanarayana , Tran., “VLSI Design of Power Gated NOR-based Content Addressable Memory”, int.jour.sci.res.mana, vol. 2, no. 10, Dec. 2017, Accessed: Sep. 06, 2025. [Online]. Available: https://www.ijsrm.net/index.php/ijsrm/article/view/1192