Design and Analysis of Folded Cascoded Operational Trans Conductance Amplifier

This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. In this design all the CMOS are in saturation region in order to optimize MOS transistor sizing. Using 0.18μm CMOS process, a fully differential folded cascode architecture has been proposed which attains the DC gain of 67.5Db, a unity-gain frequency of 500MHz, power dissipation is 125.56 µW, Phase Margin is 170degree, CMRR is 127.6dB and slew rate is 27.4 V/µs.