Abstract
This Paper Presents a Design and Analysis of Multimode Single Precision Floating Point
Arithmetic Unit Using VERILOG Hardware Description Language on FPGA. The multimode floating
point arithmetic unit have addition, subtraction, multiplication and division operations. The device used
is Zed Board Zynq Evaluation and Developed Kit (xc7z020clg484-1) on which the proposed design will
be physically verified. We design and analyse the efficient multimode floating point arithmetic unit for
IEEE 754 floating point number system, which gives a better implementation in terms of area of
hardware. We have four separate units for four different arithmetic operations, by combining addition
and subtraction unit into one and multiplication and division unit into one and by efficient optimization.
The result of this combination is to reduce the number of LUTs used in FPGA. Thus the total area of
hardware required will be reduced. The LUTs reduction is 14% and area reduction is 19%.